A2286 CMOS
Below is the CMOS RAM memory map for an A2286.
16 bytes (00h-0fh) is the real time clock, 32 bytes (10h-2Fh) is the ISA configuration data
30h until 3Fh is still unused
| Offset Hex | Feldgrösse | Funktion |
|---|---|---|
| 00h | 1 byte | RTC seconds |
| 01h | 1 byte | RTC seconds alarm |
| 02h | 1 byte | RTC minutes |
| 03h | 1 byte | RTC minutes alarm |
| 04h | 1 byte | RTC hours |
| 05h | 1 byte | RTC hours alarm |
| 06h | 1 byte | RTC day of week |
| 07h | 1 byte | RTC date day |
| 08h | 1 byte | RTC date month |
| 09h | 1 byte | RTC date year |
| 0Ah | 1 byte | Status Register A (Read/ Write Register except UIP) |
| 0Ah | Bits 0-3 | Rate selection frequency (0110 = 1.024KHz) The fore selection bits select one of 15 tapes on the 22-stage Divider,or disable the divider output. The tap selected may be used to generate an output square wave (SQW pin) and/or a interrupt. The program may do one of following: 1) enable the interrupt with. the PIE bit, 2)enable the SQW output pin with the SQWE bit, 3) enable both at the same time at the same rate,or 4) enable neather, These four bits are read/write bits which are not effected by RESET. |
| 0Ah | Bits 4-6 | Time frequency Divider (010 = 32.768KHz) DV2, DVI, DVO – Three bits are used to permit the Program to select various conditions of the 22-stage divider chain. The divider selection bits identify which of the three time-base frequencies is in use. The divider selection bits are also used to reset the divider chain. When the time/calendar is first initialized the program may start the divider at the precise Time stored in the RAM, When the divider reset is removed, the first update cycle begins one-half second later. These three read/write bits are not affected by RESET. |
| 0Ah | Bits 7 | UIP Update in Progress (0 = Date/Time can be read, 1 = Time update in Progress) The update in progress (UIP) bit is a status flag that may be monitored by the program. When UIP is a "l", the update cycle is in progress or will soon begin. When UIP is a "0", the update cycle is not in progress and will not be for at least 244 ps (for all time bases). The time, calendar, and alarm information in RAM is fully available to the program when the UIP bit is zero – it is not in transition. The UIP bit is a read-only bit, and is not affected by Reset. Writing the SET bit in Register B to a "1" inhibits any update cycle and then clears the UIP status bit. |
| 0Bh | 1 byte | Status Register B(read/write) |
| 0Bh | Bit 0 | DSE – The daylight savings enable (DSE) bit is a read/write bit which allows the program to enable two special updates (when DSE is a “1”). On the last Sunday in April the time increments from 1:59:59 AM to 3:00:00 AM. On the last Sunday in October when the time first reaches 1:59:59 AM it changes to 1:00:00 AM. These special updates do not occur when the DSE bit is a ‘JO’. DSE is not changed by any internal operations or reset. |
| 0Bh | Bit 1 | 24/12 – The 24/12 control bit establishes the format of the hours bytes as either the 24hour mode a “l” or the 12-hour mode a "0", This is a read/write bit, which is affected only by software. |
| 0Bh | Bit 2 | DM – The data mode (DM ) bit indicates whether time and calendar updates are to use binary or BCD formats. The DM bit is written by the processor program and maybe read by the program, but is not modified by any internal functions or RESET. A "1" in DM signifies binary data, while a "0" in DM specifies binary-coded-decimal (BCD) data. |
| 0Bh | Bit 3 | Bit 3 SQWE - When the square-wave enable (SQWE) bit is set to a "1" by the program, a square-wave signal at the frequeny spefified in the rate selection bits (RS3 to RSO) appears on the SQW pin. When the SQWE bit is set to a zero,the pin is held low. The state of SQWE is cleared by RESET pin. SQWE is a read/write bit. |
| 0Bh | Bit 4 | UIE – The UIE (update ended interrupt enable) bit is a read/write bit which enabled the update end flag (UF) bit in Register C to assert IRQ. The RESET pin going low or the SET bit going high clears the UIE bit. |
| 0Bh | Bit 5 | AIE – The alarm interrupt enable (AIE) is a read/write bit which when set to a "1" permits the alarm Flag (AF) bit in Register C to assert IRQ. An alarm interrupt occurs for each second that the three time bytes equal to the three alarm bytes (including a "don’t care" alarm code by binary 11XXXXX). When the AIE bit is a "0", the AF Bit does not initiate an IRQ signal. The RESET pin clears AIE to "0". The internal functions do not affect the AIE Bit. |
| 0Bh | Bit 6 | PIE – The periodic interrupt enable (PIE) bit is a read/write bit which allows the periodic-interrupt flag (PF) bit in Register C to cause the IRQ pin to be driven low. A program writes a "1" to the PIE bit in order to receive periodic interrupts at the rate specified by the RS3, RS2, RS1, and,RS0 bits in Register A. A zero in PIE blocks IRQ from being initiated by a periodic interrupt, but the periodic flag (PF) bit is still set at the periodic rate. PIE is not modified by any internal functions, but is cleared to "0" by a RESET |
| 0Bh | Bit 7 | SET – When the SET bit is a "0", the update cycle functions normally by advancing the counts once-per-second. When the SET bit is written to a "1", any update cycle in progress is aborted and the program may initialize the time and calendar bytes without an update occurring in the midst of initializing. SET is a read/write bit which is not modified by RESET or internal functions of the MC146818A. |
| 0Ch | 1 byte | Status Register C (read only) |
| 0Ch | Bit 0-3 | The unused bits of Status Register C are read as "0". They can not be written |
| 0Ch | Bit 4 | UF – The update-ended interrupt flag (UF) bit is set after each update cycle. when the UIE bit is a "1", the "1" in UF causes the IRQF bit to be a "1", asserting IRQ. UF is cleared by a Register C read or a RESET. |
| 0Ch | Bit 5 | AF – A "1" in the AF (alarm interrupt flag) bit indicates that the current time has matched the alarm time. A "1" in the AF causes the IRQ pin to go low, and a "1" to appear in the IRQF bit, when the AIE bit also is a "1". A RESET or a read of Register C clears AF. |
| 0Ch | Bit 6 | PF – The periodic interrupt flag (PF) is a read-only bit which is set to a "1" when a particular edge is detected on the selected tap of the divider chain. The RS3 to RSO bits establish the periodic rate. PF is set to a "1" independent ofthe state of the PIE bit. PF being a "1" initiates an IRQ signal and sets the IRQF bit when PIE is also a "1". The PF bit is cleared by a RESET or a software read of Register C |
| 0Ch | Bit 7 | IRQF – The interrupt request flag (IRQF) is set to a "1" when one or more of the following are true: PF=PIE="1" AF=AIE="1" UF=UIE="1" i.e. IRQF= PF*PIE+ AF*AIE+UF*UIE Any time the IRQF bit is a "1", the IRQ pin is driven low. All flag bits are cleared after Register C is read by the program or when the RESET pin is low. |
| 0Dh | 1 byte | Status Register D (read only) |
| 0Dh | Bit 0-6 | the remaining bits of Register D are unused. They cannot be written, but are always read as "0". |
| 0Dh | Bit 7 | VRT – The valid RAM and time (VRT) bit indicates the condition of the contents of the RAM, provided the power sense (PS) pin is satisfactorily connected. A "0" appears in the VRT bit when the power-sense pin is low. The processor program can set the VRT bit when the time and calendar are initialized to indicate that the RAM and time are valid. The VRT is a read only bit which is not modified by the RESET pin. The VRT bit can only be set by reading Register D. |
| 0Eh | 1 byte | Diagnostic Status |
| 0Eh | Bit 0/1 | Unused |
| 0Eh | Bit 2 | CMOS time status (0 = Time is valid, 1 = Time is invalid) |
| 0Eh | Bit 3 | Fixed disk failure (0 = good, 1 = bad) |
| 0Eh | Bit 4 | Memory size compare during POST (0 = POST memory equals configuration, 1 = POST memory not equal to configuration) |
| 0Eh | Bit 5 | Unused |
| 0Eh | Bit 6 | test for cmos valid. (Bit 6 has to store an "1". if not, store new memory size |
| 0Eh | Bit 7 | Real time clock power status (0 = CMOS has not lost power, 1 = CMOS has lost power) |
| 0Fh | 1 byte | CMOS Shutdown Status |
| 0Fh | Value 0 | manufacturing test loop |
| 0Fh | Value 1 | |
| 0Fh | Value 2 | over 1 mbyte test |
| 0Fh | Value 3 | Not in virtual mode. Error, do a shutdown and halt |
| 0Fh | Value 4 | issue boot request |
| 0Fh | Value 5 | Write "End of interrupt" to Int Controller 1 |
| 0Fh | Value 6 | unexpected |
| 0Fh | Value 7 | unexpected |
| 0Fh | Value 8 | unexpected |
| 0Fh | Value 9 | block move (int 15h) |
| 0Fh | Value 0Ah | jump to init routine |
| 10h | 1 byte | FLOPPY Bits 7-4 = Drive 0 type Bits 3-0 = Drive 1 type 0: None 1: 360K 5.25" 2: 1.2MB 5.25" 3: 720K 3.5" 4: 1.44MB 3.5" |
| 12h | 1 byte | Hard Disk Type Bits 7-4 = Hard disk 0 type Bits 3-0 = Hard disk 1 type 0 = No drive installed 15 = Type 15-47 |
| 14h | 1 byte | Installed Equipment Bit 1 = 287 installed/not installed Bits 5-4 = Primary display 00 = SPECIAL 01 = COLOR 40 10 = COLOR 80 11 = MONO Bits 7-6 = Number of floppy disks 0 = 1 floppy disk 1 = 2 floppy disks |
| 15h 16h |
2 byte | 0-640K MEMORY SIZE Base Memory Low Byte Base Memory High Byte |
| 17h 18h |
2 byte | Extended Memory Low Byte Extended Memory High Byte |
| 19h | 1 byte | Extended HD1 Type (15-48) |
| 1Ah | 1 byte | Extended HD2 Type(15-48) |
| 1Bh | 1 byte | Unused |
| 1Ch | 1 byte | Unused |
| 1Dh | 1 byte | Unused |
| 1Eh | 1 byte | Unused |
| 1Fh | 1 byte | Unused |
| 20h | 1 byte | COMMODORE |
| Bit 1,0 -- Default system speed 00 -- 6 MHz 01 -- 8 MHz 10 -- 12 MHz |
||
| Bit 3,2 -- On board LPT address 00 -- Off 01 -- 3BCH 10 -- 378H 11 -- 278H |
||
| Bit 5,4 -- On board COM address 00 -- Off 01 -- 3F8H 10 -- 2F8H |
||
| Bit 6 -- On board mouse 0 -- Disabled 1 -- Enabled |
||
| Bit 7 -- 6 MHz hard disk IO feature 0 -- Disabled 1 -- Enabeled |
||
| 2Eh 2Fh |
2 byte | CMOS Checksum High Byte - Most significant byte CMOS Checksum Low Byte - Least significant byte |
Last update: 21.05.2022