Janus IO Memory Map

AMIGA I/O MEMORY MAP

(REGISTER DESCRIPTION)

PC SIDE

System Status Register:

How to Enable/Disable Interrupts from Amiga to PC A write access to this register (i/o location 62 hex) forces a /SYSINT interrupt on the AMIGA side
A write access to bit 6 of i/o location 379 hex enables/disables the AMIGA forced interrupts IRQ1 (keyboard), 1RQ3 (serial interface COM2) and IRQ7 (parallel interface LPT1) as follows:

Note:

The access to i/o location 379 hex is enabled if PARON is high. That is, the AMIGA has to write a "1" to MODE REGISTER bit 1. (See 'Amiga Mode Register.')
The following initialization routine must be used to allow an external printer card on the pc side:

• AMIGA: set MODE REGISTER bit 1 to "1" ; switch parallel interface on
• PC : set i/o location 379 hex bit 6 to "0"; keyboard and serial interr. off
• AMIGA: set MODE REGISTER bit 1 to "0" ; switch parallel interface off

Now the keyboard and the serial interface emulation is enabled, the parallel interface emulation is disabled.

HOW to Clear an Asserted Interrupt Signal

AMIGA SIDE

All registers on the memory locations 1FFF0 TO 1FFFF are only accessable from the AMIGA side.

AMIGA ACCESS: Amiga Interface Offset Address = Base Addr.

• Base Addr. + (00000 - 1FFFF) : Byte Access
• Base Addr. + (20000 - 3FFFF) : Word Access
• Base Addr. + (40000 - 5FFFF) : Graphic Access
• Base Addr. + (60000 - 7FFFF) : I/O Register Access

All Registers on the Memorylocations 1FFF0 to 1FFFF are only accessable from the AMIGA side.

Amiga Interrupt Status Register (R/O)(1FFF1/7FFF1)

Reading this register returns the interrupt events caused on PC accesses as follows:

The event was valid if the bit is set to " 1". After reading the register all bits turns to "0" automatically and the interrupt flag will be negated.

 PC Interrupt Status Register (R/O) (1FFF3/7FFF3)

Reading this register returns the pending PC interrupts on the lower nibble. The PC interrupt is asserted as shown by the corresponding bit in the table.

Bit 1 and bit 2 (IRQ3_a and lRQ3_b) are externally "ORed" to IRQ3

Negate PC Reset (R/O)(1FFF5/7FFF5)

A read access to this register negates the PC reset line and allows the PC to start the boot procedure. On power-on the PC reset line is asserted (default).

Mode Register (R/W) (1FFF7/7FFF7)

Reading this register returns system configuration information

Writing to this register sets system configuration information

 select the PC/AT memory bank

Interrupt Mask Register (R/W)(1FFF9/7FFF9)

You can mask each PC interrupt event separately by writing a "1" to the corresponding bit as shown below.

PC Interrupt Control Register (R/W) (1FFFB/7FFFB)

A PC interrupt can be forced by writing a "0" to the corresponding bit of the lower nibble except the keyboard interrupt, which can be asserted by writing a "1", as shown below:

Bit 1 and bit 2 (IRQ3_a and lRQ3_b) are externally "ORed" to IRQ3

Control Register (R/W)(1FFFD/7FFFD)

All control function will be done by writing a "0" to the corresponding bit Only bits 0 to 4 are used.

Keyboard Register (R/W) (1FFFF/7FFFF)

Keyboard emulation is done by writing a character to this register and then asserting a "1" to bit 0 of the PC INTERRUPT CONTROL REGISTER.

Last Update: 05.06.2022