A2286 Errorcodes
Die Errorcodes und Excepions werden auf Port 2F8h (LPT1) ausgegeben.
Benötigt wird mindestens das BIOS A2286 4.3 A1k Rev. 0.1h
| Errorcode | Kurzbechreibung | Bechreibung |
|---|---|---|
| 01h | cpu check | checks 8088 Flags, ALU and Registers |
| 02h | shutdown | this Routine checks to see if a Shutdown has been issued, and if so branches to the proper Routine. the Branch Information is stored in the CMOS Memory. a Shutdown is executed to exit protected Mode. |
| 03h | eprom checksum test | verify contents of EPROM by adding all bytes and checking for a result of zero. compensation byte to make sum zero is stored at ffff. |
| 04h | test DMA Page Registers | |
| 62h | Read, Write compare DMA Register fail | Read, Write compare DMA Register fail afterwards CPU HLT(since Rev 0.1b) |
| 05h | timer test | test the 8254 Timer and make sure it Counts |
| 63h | TIMER 0 NOT COUNTING | afterwards CPU HLT(since Rev 0.1d) |
| 64h | TIMER 0 TOO FAST | afterwards CPU HLT(since Rev 0.1d) |
| 65h | TIMER 0 TOO SLOW | afterwards CPU HLT(since Rev 0.1d) |
| 66h | TIMER 2 NOT COUNTING | afterwards CPU HLT(since Rev 0.1d) |
| 67h | TIMER 2 TOO FAST | afterwards CPU HLT(since Rev 0.1d) |
| 68h | TIMER 2 TOO SLOW | afterwards CPU HLT(since Rev 0.1d) |
| 06h | test Refresh | timer and DMA Chips are setup to cause Refreshcycles to occur every 15.1 Microseconds. |
| 69h | No DRAM REFRESH OCCURING (Timer 1 fault) | afterwards CPU HLT(since Rev 0.1d) |
| 6Ah | synchronize with the amiga | wait for lock byte of janusbase |
| 07h | Test keyboard controller(8042) | |
| 6Bh | Cant empty UPI Buffer | afterwards CPU HLT(since Rev 0.1d) |
| 6Ch | 8042 Diagnostic Command failed | afterwards CPU HLT(since Rev 0.1d) |
| 08h | test first 128k of RAM | writes, reads and verifies 128k RAMBlocks clears Memory after Test |
| 60h | Test 128k fail | if Test 128k fail afterwards CPU HLT(since Rev 0.1b) |
| 61h | write RamSize in CMOS | writing RamSize to CMOS afterwards CPU HLT(since Rev 0.1b) |
| 09h | setup video | |
| 0Ah | test ram from 128k to till 640k | writes, reads and verifies 128k RAMBlocks first pass writes Address into Data (no invert). second pass writes complement of Address into Data (invert). configure first 640k of Memory. clear 128k to 640k RAM |
| 0Bh | dma controller #1 register test | write current Address and Wordcount Registers for each Channel with a unique Pattern. read the Registers and check if same as written pattern. setup the DMA Controller |
| A0h | DMA 1 error | afterwards CPU HLT(since Rev 0.1b) |
| 0Ch | dma controller #2 register test | write current Address and Wordcount Registers for each Channel with a unique Pattern. read the Registers and check if same as written pattern. |
| A1h | DMA 2 error | afterwards CPU HLT(since Rev 0.1b) |
| 0Dh | interrupt controller #1 test | read,write the intr mask reg (IMR) with AA and 55 patterns. setup the Interruptcontroller and verify that no interrupts occur if the IRM is set to FFh. verify that a Timerinterrupt occurs. |
| A2h | Interrupt controller 1 error | afterwards CPU HLT(since Rev 0.1d) |
| 0Eh | interrupt controller #2 test | Read,Write the intr mask reg (IMP) with AA and 55 patterns. setup the Interruptcontroller and verify that no Interrupts occur if the IMR is set to FFh. |
| A3h | Interrupt controller 2 error | afterwards CPU HLT(since Rev 0.1d) |
| 0Fh | test PIO | |
| A4h | PIO error | afterwards CPU HLT(since Rev 0.1d) |
| 10h | test RAMparity | |
| A5h | Parity error | afterwards CPU HLT(since Rev 0.1d) |
| 11h | test CMOS Clock Calendar | test CMOS Clock Calendar for 1. Battery failure 2. Checksum failure |
| 12h | test for Manufacturing test mode | |
| 13h | setup Interruptcontroller and move the Vectors into RAM | |
| 14h | keyboard test | |
| 15h | test and configure parallel ports | |
| 16h | serial configuration | |
| 17h | configure Memory to 640k | |
| 18h | configure Memory over 1mb | |
| 19h | configure Keyboard | |
| 1Ah | configure Floppy Disk | |
| 1Bh | configure the Hard Disk | |
| 1Ch | configure Gamecard | |
| 1Dh | configure 80287 | |
| 1Fh | generate new CMOS Checksum | and save it in CMOS Ram |
| 21h | initilize the Romdrivers | (including Harddisk) |
| 24h | test CMOS Clock | |
| B0h | BAD BATTERY STATUS | afterwards CPU HLT(since Rev 0.1d) |
| B1h | Clock UPDATE STUCK | afterwards CPU HLT(since Rev 0.1d) |
| B2h | CMOS MEMORY ERROR | afterwards CPU HLT(since Rev 0.1d) |
| 25h | cause a Shutdown | for manufacturing Testloop |
| 26h | test Memory over 1 Mbyte | first check if we do have Memory over 1 Mbyte |
Last Update: 02.04.2024